This paper is published in Volume 3, Issue 5, 2018
Area
Embedded Systems
Author
Revathi Gunthakalla
Org/Univ
Vishnu Sree Institute of Technology, Hyderabad, Telangana, India
Pub. Date
30 April, 2018
Paper ID
V3I5-1137
Publisher
Keywords
VLSI, High speed, Low Power consumption, MHS-Domino gates, CMOS, Clock gating etc

Citationsacebook

IEEE
Revathi Gunthakalla. Methodologies for high-speed and low-power VLSI design, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARnD.com.

APA
Revathi Gunthakalla (2018). Methodologies for high-speed and low-power VLSI design. International Journal of Advance Research, Ideas and Innovations in Technology, 3(5) www.IJARnD.com.

MLA
Revathi Gunthakalla. "Methodologies for high-speed and low-power VLSI design." International Journal of Advance Research, Ideas and Innovations in Technology 3.5 (2018). www.IJARnD.com.

Abstract

High-Speed and Low-power are the major challenges for today’s electronics industries. Power dissipation is an important consideration in terms of Speed/Performance and space for VLSI Chip design. Power management techniques are generally used to designing low power circuits and systems. This thesis presents the various VLSI Design Methodologies for high Speed and Low power management techniques that can meet future challenges to designs low power high speed/performance circuits, algorithm level design. It also describes the many issues regarding circuits design at architectural, logic and device levels and presents various techniques to overcome difficulties.
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