Most operating systems assign a page table for each process. The page table keeps track of where the virtual pages are saved in the physical memory. The virtual memory scheme would suffer the effect of doubling the memory access time. We can reduce the time taken to access the page table again and again by using Translation Lookaside Buffer (TLB). But, when we don’t find the page frame number inside the TLB, the CPU has to access main memory for it. One problem is where the needed information itself actually is in a cache, although the information for virtual-to-physical translation is not in a TLB. A TLB miss can be more important due to the need for not just a load from main memory. The paper priority explains the concept of TLB miss handling because the translation is performed quickly without having to consult the page table. This paper aims to discuss how hardware can help us make address translation faster and how to provide MIPS R4000 architecture on TLB to translate virtual address into physical address. So, we will describe TLB Control Flow Program to avoid TLB miss as much as we can. We will explain that examine an array in a tiny address trace. Also note the role that the array access will suffer even fewer misses.